The market did not sell Micron because a Chinese company started making high-bandwidth memory. It sold Micron because a Chinese company listed. ChangXin Memory Technologies closed its first session on Shanghai’s STAR Market on 27 July 2026 at 49 yuan, up 465.8% from an 8.66 yuan offer price, after raising 57.92 billion yuan — about $8.6bn — in the largest mainland Chinese listing since Agricultural Bank of China in 2010. Within hours SanDisk was down 12%, Western Digital 7%, SK Hynix’s ADRs 6% and Micron 5%. Yet the document that triggered all of it contains no funded HBM project. CXMT’s prospectus allocates 29.5 billion yuan across three named projects — 13bn for DRAM technology upgrades, 9bn for next-generation DRAM research and 7.5bn for memory wafer line upgrades — and not one of them is high-bandwidth memory.
That is the gap worth trading. The part of the memory market that is actually driving the AI cycle is HBM, and by the filing’s own allocation CXMT is not spending IPO money on it. The threat the prospectus does describe is real, large and completely different in shape: conventional DDR5 and LPDDR at scale, funded by the Chinese state, sold at a discount, and produced at a cost per bit that independent analysis puts more than 30% above Samsung, SK Hynix and Micron. Investors marked down the AI memory complex for a filing that funds the commodity end of the business. Micron closed at $868.52 on 11 August 2026, 28.4% below its 25 June closing high of $1,213.56 — and the single most useful number in this whole story is not 466%. It is 93%.
Key facts
- CXMT closed its debut at 49 yuan, +465.8% on an 8.66 yuan offer price, with an intraday range of 38.11–55.03 yuan (a peak of roughly +535%) and 141.19bn yuan of turnover — Implicator.ai, 27 July 2026
- The IPO raised 57.92bn yuan (~$8.6bn), up to 66.61bn yuan with over-allotment, valuing CXMT near 3.3 trillion yuan and making it China’s most valuable A-share company — TechNode, 27 July 2026
- The prospectus names 29.5bn yuan of projects and no HBM line: 13bn DRAM technology upgrade, 9bn next-generation DRAM research, 7.5bn wafer manufacturing line upgrade — Tom’s Hardware, 27 July 2026
- CXMT’s DDR5 cost per bit runs more than 30% above Samsung, SK Hynix and Micron, while its DRAM ASP in Q1 2026 sat only 5–10% below theirs — SemiAnalysis
- HBM will absorb roughly 22% of total DRAM wafer input in 2026 but supply only about 9% of DRAM bits — TrendForce, 2 June 2026
- Micron’s fiscal Q3 2026 (ended 28 May): revenue $41.46bn, up 346% year on year, GAAP gross margin 84.6%, operating income $33.32bn — Micron, 24 June 2026
- Chip stocks shed more than $1 trillion in the week of the listing; SK Hynix lost $176bn, Samsung $173bn and Micron $113bn — CNBC, 29 July 2026
What the filing actually funds
Read the use-of-proceeds section and the strategy is unambiguous. Of the 29.5bn yuan CXMT itemises, roughly 70% goes to wafer lines and DRAM process work. The remaining roughly 28bn yuan of the raise is not attached to a named project at all; it is described as working capital. Nothing in that structure is dedicated to high-bandwidth memory, the stacked, through-silicon-via product that sits next to an AI accelerator and that Nvidia, AMD and every hyperscaler buy by the tonne.
This needs a precise reading, because the easy version of the claim is wrong. “No HBM project in the prospectus” is not the same as “no HBM programme.” CXMT has an HBM effort. SemiAnalysis models it at roughly 5,000 wafer starts per month dedicated to HBM in 2025, rising to about 30,000 in 2026 and 55,000 in 2027. What the filing tells you is where the $8.6bn of fresh public capital is pointed — and it is pointed at conventional DRAM capacity and conventional DRAM process development. When a company raises the largest sum in the mainland market in sixteen years and does not ring-fence any of it for the product category the entire industry narrative is built on, that is a disclosure about priorities.
It is also a disclosure about capability. SemiAnalysis puts CXMT’s HBM3 8-high front-end yield near 35% and back-end yield near 70%, an overall yield of roughly 25%. At that level HBM is not a product line; it is an experiment being run at industrial scale. The firm’s analysis suggests CXMT may skip HBM3 entirely and target HBM3E 8-high and 12-high to line up with mainstream accelerator demand — a sensible plan, and one that pushes meaningful volume out past the horizon most of the 27 July sellers were trading.
The number that matters is 93%, not 466%
Here is the synthesis that the debut-day coverage missed. On bottom-up estimates from Citrini Research, widely reported at the time, CXMT will finish 2026 with roughly 350,000 DRAM wafer starts per month against Micron’s roughly 375,000 — about 93% of Micron’s wafer capacity. SemiAnalysis models a similar path: about 265,000 wafer starts per month at the end of 2025, 350,000 at the end of 2026, 420,000 by the end of 2027 and 500,000 by the end of 2028.
Now put that next to market share. CXMT held roughly 8% of the DRAM market in 2025, fourth behind Samsung at about 36%, SK Hynix at about 29% and Micron at about 24%, on the figures cited across coverage of the listing by 24/7 Wall St and Tom’s Hardware. Different trackers put the incumbents a percentage point or two either side of those numbers, but the ranking is not in dispute.
Allow for the timing mismatch — 2025 share against end-2026 capacity — and the shape still holds: a company running something close to nine-tenths of Micron’s wafer count commands roughly a third of Micron’s revenue share. Wafers are not bits, and bits are not dollars. CXMT’s 2025 revenue was around $8.6bn on SemiAnalysis estimates. Micron booked $41.46bn in a single quarter.
The mechanism is process node. Micron’s 1-gamma is its first DRAM node to use EUV lithography and delivers more than 30% better bit density per wafer than 1-beta alone; it is the company’s mainstream node for 2026 and is already ramping in 16Gb LPDDR5X at a leading smartphone customer. CXMT is running a G4 process, roughly 1z-equivalent, and moving to G5, roughly 1a-equivalent — two full generations behind, and doing it without EUV. That is not a rounding error in cost. It is the 30%-plus cost-per-bit gap, expressed in physics.
Is the cost gap structural or a learning curve?
This is the question that decides whether the 27 July reaction was early or simply wrong, and the honest answer is: partly each.
The learning-curve part is real. SemiAnalysis notes that CXMT’s G5 node, the 1a-equivalent, “can theoretically continue advancing without EUV akin to Micron in 1a process node” — Micron itself built 1a on deep-ultraviolet multipatterning. Yields improve with volume, and CXMT is about to have an enormous amount of volume. Its revenue went from roughly $1.2bn in 2023 to $3.3bn in 2024 to $8.6bn in 2025, and it booked around $7.3bn in Q1 2026 alone. Q1 2026 gross margins near 70% show what a shortage does to a high-cost producer: the cost disadvantage stops mattering when everything sells.
The structural part is the ceiling. Multipatterning gets you to 1a. It does not get you economically to 1b, 1c or 1-gamma, where the incumbents already are and where HBM4E is being built. Every additional mask layer costs cycle time, tool time and yield. Micron shipped its first EUV DRAM node and is now sampling 256GB DDR5 RDIMMs on 1-gamma with 3D die stacking. CXMT’s roadmap, absent EUV access, ends somewhere short of that. So the gap narrows on conventional DDR5 and widens at the leading edge — which is exactly the split that the prospectus’s spending plan implies CXMT already understands about itself.
There is a genuine counter-argument, and it deserves stating rather than dodging. TrendForce reported that HBM wafer revenue fell below the profitability of 64GB DDR5 RDIMM wafers in Q1 2026 — for a stretch this year, a wafer of conventional server DRAM earned more than a wafer of HBM. If that persists, CXMT’s decision to pour public money into conventional DRAM lines is not a confession of weakness. It is a bet on the most profitable wafer in the industry. Anyone dismissing the CXMT threat on “it’s only DDR5” grounds should sit with that number for a moment.
What the incumbents’ own numbers say
Micron’s fiscal Q3 2026, reported on 24 June, is the cleanest available read on what is actually at stake. Revenue of $41.46bn against $9.30bn a year earlier. GAAP gross margin of 84.6%, non-GAAP 84.9%. Operating income of $33.32bn, 80.4% of revenue. Adjusted free cash flow of $18.30bn. Guidance for fiscal Q4 of $50.0bn ± $1.0bn at roughly 86% gross margin.
The segment split is where the CXMT question gets answered. Cloud Memory — the HBM-heavy business — did $13.77bn at an 83% gross margin. Core Data Center did $11.52bn at 87%. Mobile and Client did $11.52bn at 87%. Automotive and Embedded did $4.63bn at 79%. Roughly a third of Micron’s revenue sits in the pool CXMT’s prospectus does not fund. Most of the rest sits in pools it does — and those pools are earning 87% gross margins, which is precisely the kind of number that attracts a state-backed entrant with a cost disadvantage and patient capital.
“Micron’s record fiscal Q3 financial results and even stronger outlook for Q4 reflect the strategic value of memory in the AI era,” said Sanjay Mehrotra, Chairman, President and CEO of Micron Technology, in the results release. “We believe our multi-year Strategic Customer Agreements will significantly enhance the durability and predictability of Micron’s strong financial performance.” Those agreements matter more than any market-share table: contracted multi-year volume is the one asset a new entrant cannot underbid, because the capacity is already sold.
SK Hynix told the same story from the other side and got punished for it. Its Q2 2026, reported at the end of July, showed 79.3 trillion won of revenue and 60.5 trillion won of operating profit — a 76% operating margin, with revenue up 257% and operating profit up 557% year on year. It then guided 2026 capital expenditure roughly 50% higher, to at least 45 trillion won (about $31bn). Record earnings, record spending, and a share price that fell anyway. Our coverage of that session — the KOSPI trading halt as SK Hynix’s ADR broke $140 — is the clearest evidence that CXMT was not the only thing moving memory that week.
Quantifying the threat horizon
If you want one framework for the next eighteen months, use the wafer-versus-bit split. TrendForce’s June 2026 data has HBM taking about 18% of total DRAM wafer input at the end of 2025, roughly 22% at the end of 2026 and roughly 30% by the end of 2027, while delivering about 8%, 9% and 13% of total DRAM bit supply across those same years. HBM eats wafers and returns few bits. That is what makes it scarce, expensive and — for now — structurally protected from a competitor that cannot build it.
TrendForce is explicit about the second-order effect: “As HBM generations continue evolving in 2027, with larger die sizes and simultaneously rising demand, the crowding-out effect on conventional DRAM capacity is expected to intensify further.” Read that alongside CXMT’s plan and the strategic logic snaps into focus. The incumbents are being pulled toward HBM by margin and by contract. That vacates conventional DRAM capacity. CXMT is spending $8.6bn of public money to be standing there when it does.
So the realistic threat schedule looks like this. Through 2027, CXMT pressures conventional DDR5, LPDDR and DDR4 pricing in China and in price-sensitive export markets, with a cost handicap that only works because Beijing is willing to fund it — Hefei state venture capital covered roughly 80% of the first phase of the project, 14.4bn yuan of 18bn, and state entities hold more than 30% of the company after the IPO. From 2028, if HBM3E yields move from experimental to industrial, the challenge starts reaching the AI pool. Nothing in the prospectus accelerates that; the IPO money is being spent somewhere else.
The political variable is the fastest-moving one
The most underpriced risk in this story is not technological. CXMT remains on the US Department of Defense’s Section 1260H list of Chinese military companies. The Pentagon published an updated list on 8 June 2026 adding 65 entities; CXMT and Yangtze Memory both stayed on it, after a February draft that had briefly dropped them was withdrawn without explanation, as WilmerHale documented.
The 1260H list is not the Entity List. It restricts certain US investment activity and carries reputational weight; it does not by itself bar an American company from buying CXMT parts. Which is why the Apple story matters so much: Apple has been testing CXMT DRAM for China-market devices and has been seeking US approval to source from CXMT as memory prices spiralled. A single tier-one qualification would do more for CXMT’s position than 466% ever did, and it would arrive as a headline, not as a capacity ramp. That is the asymmetry investors in Micron’s bull and bear case should be watching, and it is why memory inflation is already showing up in downstream guidance at firms like Qualcomm.
Even inside China, the price was not universally believed. “At such a price, I don’t dare to hold, or buy the stock,” Wu Zhou of Shenzhen Deyuan Investment said of the debut, in comments carried in coverage of the listing. The retail tranche was oversubscribed 212 times and 66.4% of the free float turned over on day one. That is not a valuation; that is an auction.
Three things to watch
One: the share price already round-tripped the debut, and that tells you the market has partly worked this out. Micron closed at $900.20 on 27 July — down 2.25% on the day, not the 5% that ran in the intraday headlines — then fell to $739.00 by 29 July as SK Hynix’s capex guidance and broader AI-spending fears took over, and has since recovered to $868.52. Two weeks after the listing, Micron sits within 4% of where it closed on debut day. The CXMT-specific damage was largely a one-session repricing; the durable damage came from the capex cycle. Expect the next leg to be set by hyperscaler capex commentary, not by Shanghai.
Two: the first genuinely load-bearing catalyst is an HBM3E qualification, not a capacity announcement. Wafer starts are easy to model and easy to announce. Yields are not. Until CXMT demonstrates HBM3E 8-high at commercial yield with a named accelerator customer, capacity headlines should be treated as conventional-DRAM news and priced against Micron’s Mobile and Client and Core Data Center segments — not against Cloud Memory.
Three: the cost gap will narrow before it closes, and the narrowing is the trade. If DRAM contract prices normalise from the extraordinary levels that produced 84.6% gross margins at Micron and 76% operating margins at SK Hynix, a producer running 30%-plus above the cost curve stops printing 70% gross margins very quickly. State support can absorb that; it cannot make it invisible. The moment to reassess the CXMT threat is not the next capacity headline — it is the first quarter in which memory pricing falls and CXMT keeps shipping anyway. That is also when the wider AI chip complex gets its real stress test.
The 466% was a story about Chinese domestic liquidity and self-sufficiency policy meeting a supply-constrained IPO with a 212-times-oversubscribed retail tranche. It was not, on the evidence of the document itself, a story about high-bandwidth memory. Anyone who sold Micron, SanDisk or Samsung on 27 July because China was coming for HBM traded a headline against a filing that says otherwise. The filing may still be wrong about the future. It is not ambiguous about the present.
FAQ
Did CXMT really close up 466% on its Shanghai debut?
Yes. CXMT closed its first STAR Market session on 27 July 2026 at 49 yuan against an 8.66 yuan offer price, a gain of 465.8%, having traded as high as 55.03 yuan intraday — roughly +535% at the peak. The wide range of figures quoted in coverage (465%, 466%, 531%, 535%) reflects whether the source is citing the close or an intraday print.
Does CXMT’s prospectus really contain no HBM project?
The prospectus itemises 29.5bn yuan across three projects — DRAM technology upgrades, next-generation DRAM research and memory wafer line upgrades — none of which is a high-bandwidth memory project. That is not the same as saying CXMT has no HBM programme; independent analysts model roughly 30,000 HBM wafer starts per month in 2026. It means the IPO proceeds are not earmarked for HBM.
How much did Micron actually fall on the day CXMT listed?
Micron traded down about 5% intraday on 27 July 2026 and closed at $900.20, a fall of 2.25% from the previous close of $920.95. The larger damage came later in the week: Micron closed at $739.00 on 29 July, roughly 19.8% below its 24 July close, as SK Hynix’s capex guidance and broader AI-spending fears hit the sector.
Why does a 30% cost-per-bit disadvantage matter if CXMT is profitable?
It matters at the next down-cycle, not this one. With DRAM in acute shortage, CXMT posted roughly 70% gross margins in Q1 2026 despite the cost gap, because scarce supply sells at whatever price clears. When contract prices normalise, a producer sitting 30% above the cost curve loses margin far faster than one sitting on it.
Is CXMT banned from selling chips to US companies?
No. CXMT is on the US Department of Defense’s Section 1260H list of Chinese military companies, reaffirmed in the 8 June 2026 update. That list restricts certain US investment activity and carries reputational weight but is not the Commerce Department’s Entity List, and it does not by itself prohibit American firms from buying CXMT products. Apple has been testing CXMT DRAM and seeking US approval to source from the company.
What share of the DRAM market is HBM?
By volume, less than you would guess from the headlines. TrendForce estimates HBM will consume roughly 22% of total DRAM wafer input in 2026 while supplying only about 9% of total DRAM bits, rising to roughly 30% of wafer input and 13% of bits in 2027. HBM’s disproportionate share of industry profit comes from price, not from volume.
This article is analysis and reporting, not investment advice. Micron’s last close of $868.52 is as of 11 August 2026. Share prices, DRAM contract prices and capacity estimates move quickly; verify current figures before acting on any of them.